The present invention relates to a method of producing a Schottky varicap using the following steps:
(a) providing an epitaxial layer on a semiconductor substrate, the epitaxial layer having an upper surface and being of a first conductivity type;
(b) implanting atoms to provide the epitaxial layer with a predetermined varicap doping profile;
(c) providing a Schottky electrode on the epitaxial layer.
Such a method is known from JP-A-09/275217. In the known method, impurity atoms are implanted in the epitaxial layer to generate a Gaussian distribution. The surface of the epitaxial layer is etched until the peak concentration of the Gaussian distribution is reached. Then, the Schottky electrode is deposited on the epitaxial layer. An ohmic electrode is deposited on the opposing side of the substrate. This method renders Schottky varicaps but is not well suited to be used in an integrated process in which also other components are formed at the same time. Moreover, since the epitaxial layer is etched itself damage may easily occur and it is difficult to obtain a pure surface on which the Schottky electrode is deposited.
In several applications, one desires to employ a high quality varicap for integration in a RF-process. Requirements regarding the varicaps may be e.g.:
1. by adding a varicap to the process, only a minimum additional complexity is accepted, preferably, no more than 1 additional mask;
2. full freedom to apply required doping profiles in the varicap since they determine both the tuning range and the quality factor of the varicap for a given frequency;
3. after the varicap doping profile has been made, no long-lasting high temperature step is allowed in order to avoid further diffusion into the epitaxial layer;
4. full freedom to apply doping profiles in other components;
5. low reverse bias leakage current in the varicap.
It is observed that it is known as such to produce Schottky barrier diodes simultaneously with bipolar transistors on a single substrate, cf. e.g. U.S. Pat. No. 5,109,256 and U.S. Pat. No. 5,583,348. The application of guard rings is also known from these documents.
The object of the invention is to provide a method of producing a varicap that can be integrated on a single chip with other semiconductor components like bipolar transistors and high density capacitors. Basically, the inventor of the invention has found that the requirements listed above can be met by a Schottky varicap. Therefore, the invention provides a method of producing a Schottky varicap using the following steps:
(a) providing an epitaxial layer on a semiconductor substrate, the epitaxial layer having an upper surface and being of a first conductivity type;
(b) providing an insulating layer, and patterning the insulating layer to provide an insulating film on a predetermined area of the surface of the epitaxial layer, the insulating film comprising an oxide film contacting the epitaxial film on the predetermined area and a silicon nitride film above the oxide film;
(c) depositing a polysilicon layer of a second conductivity type;
(d) applying a first high temperature step to diffuse a guard ring of the second conductivity type into the epitaxial layer around the first predetermined area;
(e) removing a predetermined portion of the polysilicon layer to expose the first silicon nitride film;
(f) implanting atoms through at least the first oxide film to provide the epitaxial layer with a predetermined varicap doping profile;
(g) applying a second high temperature step to anneal and activate the varicap doping profile;
(h) removing the first oxide film to provide an exposed area of the upper surface of the epitaxial layer with the predetermined varicap doping profile;
(i) providing a Schottky electrode on the exposed area.
With such a method a Schottky varicap can be produced that shows a very low reverse bias leakage current due to the guard ring and due to the application of the insulating layer comprising an oxide layer and a nitride layer during the manufacturing process. The latter layers remain on the epitaxial surface until a very late process stage and protect the epitaxial layer from other process steps like plasma etching necessary for producing other components on the epitaxial layer like transistors and high density capacitors. Thus, the Schottky electrode will be deposited on a very pure portion of the epitaxial layer which greatly enhances the varicap performance. Moreover, the doping profile of the varicap can be controlled to a large extent. Consequently, the tuning range and quality factor of the Schottky varicap can be controlled optimally.
If desired, the Schottky varicap can be connected such that it operates as a forward biased diode.
The method of the invention can advantageously be used to produce simultaneously a Schottky varicap and a transistor on a single chip. Therefore, the invention also relates to a method of producing a Schottky varicap simultaneously with a transistor on a single chip using the following steps:
(a) providing an epitaxial layer on a semiconductor substrate, the epitaxial layer having an upper surface and being of a first conductivity type;
(b) providing an insulating film on a first predetermined area of the surface of the epitaxial layer, the insulating film comprising a first oxide film contacting the epitaxial layer and a first silicon nitride film above the first oxide film;
(c) depositing a polysilicon layer of a second conductivity type;
(d) providing an opening in the polysilicon layer at a second predetermined area of the surface of the epitaxial layer;
(e) providing a base diffusion region of a second conductivity type in the epitaxial layer below the opening;
(f) applying a first high temperature step to diffuse a guard ring of the second conductivity type into the epitaxial layer around the first predetermined area and to diffuse a base contact region adjacent to the second predetermined area;
(g) providing an emitter contact in the opening, which emitter contact is electrically insulated from the polysilicon layer;
(h) removing a predetermined portion of the polysilicon layer to expose the first silicon nitride film;
(i) implanting atoms through at least the first oxide film to provide the epitaxial layer with a predetermined varicap doping profile;
(j) applying a second high temperature step to diffuse an emitter region into the epitaxial layer, and to anneal and activate the varicap doping profile;
(k) removing the first oxide film to provide an exposed area of the upper surface of the epitaxial layer with the predetermined varicap doping profile;
(l) providing a Schottky electrode on the exposed area.
However, the invention can also be used to produce a Schottky varicap simultaneously with a high density capacitor, which method uses the following steps:
(a) providing an epitaxial layer on a semiconductor substrate, the epitaxial layer having an upper surface and being of a first conductivity type;
(b) implanting atoms in a second predetermined area of said upper surface to provide said epitaxial layer in said second predetermined area with a high doping concentration;
(c) providing an insulating layer, and patterning the insulating layer to provide a first insulating film on a first predetermined area of the surface of the epitaxial layer and a second insulating film on a second predetermined area of the surface of the epitaxial layer, the first insulating film comprising a first oxide film contacting the epitaxial film on the first predetermined area and a first silicon nitride film above the first oxide film, the second insulating film comprising a second oxide film contacting the epitaxial film on the second predetermined area and a second silicon nitride film above the second oxide film;
(d) depositing a polysilicon layer of a second conductivity type;
(e) applying a first high temperature step to diffuse a guard ring of the second conductivity type into the epitaxial layer around the first predetermined area;
(f) removing a predetermined portion of the polysilicon layer to expose the first silicon nitride film;
(g) implanting atoms through at least the first oxide film to provide the epitaxial layer with a predetermined varicap doping profile;
(h) applying a second high temperature step to anneal and activate the varicap doping profile;
(i) removing the first oxide film to provide an exposed area of the upper surface of the epitaxial layer with the predetermined varicap doping profile;
(j) providing a Schottky electrode on the exposed area.
In a very advantageous embodiment, the present invention provides a method in which a Schottky varicap, a high density capacitor and a transistor are simultaneously formed. The steps included in this method are:
(a) providing an epitaxial layer on a semiconductor substrate, the epitaxial layer having an upper surface and being of a first conductivity type;
(b) implanting atoms in a second predetermined area of said upper surface to provide said epitaxial layer in said second predetermined area with a high doping concentration;
(c) providing an insulating layer, and patterning the insulating layer to provide a first insulating film on a first predetermined area of the surface of the epitaxial layer and a second insulating film on a second predetermined area of the surface of the epitaxial layer, the first insulating film comprising a first oxide film contacting the epitaxial film on the first predetermined area and a first silicon nitride film above the first oxide film, the second insulating film comprising a second oxide film contacting the epitaxial film on the second predetermined area and a second silicon nitride film above the second oxide film;
(d) depositing a polysilicon layer of a second conductivity type;
(e) providing an opening in the polysilicon layer at a third predetermined area of the surface of the epitaxial layer;
(f) applying a first high temperature step to diffuse a guard ring of the second conductivity type into the epitaxial layer around the first predetermined area and to diffuse a base contact region adjacent to the third predetermined area;
(g) providing a base diffusion region of a second conductivity type in the epitaxial layer below the opening;
(h) providing an emitter contact in the opening, which emitter contact is electrically insulated from the polysilicon layer;
(i) removing a predetermined portion of the polysilicon layer to expose the first silicon nitride film;
(j) implanting atoms through at least the first oxide film to provide the epitaxial layer with a predetermined varicap doping profile;
(k) applying a second high temperature step to diffuse an emitter region into the epitaxial layer, and to anneal and activate the varicap doping profile;
(l) removing the first oxide film to provide an exposed area of the upper surface of the epitaxial layer with the predetermined varicap doping profile;
(m)providing a Schottky electrode on the exposed area.
A method of providing transistors and high density capacitors on a single chip is known per se. Compared with this known method only one additional mask is needed, i.e., the mask used in the step of removing the predetermined portion of the polysilicon layer to expose the first nitride film in the varicap area.
In an embodiment of these inventive methods, the predetermined varicap doping profile is obtained by implanting 4xc3x971012 cmxe2x88x922, 30 keV phosphor atoms in the step of implanting atoms through the first oxide film, and the epitaxial layer has a 5xc3x971015 cmxe2x88x923 arsenic doping level. Such a varicap is optimized for a frequency of 1.8 GHz, has a tuning range of about 10 using a voltage swing of 0-3 V. The quality factor is at least 14. In an alternative embodiment of these inventive methods, the predetermined varicap doping profile is obtained by implanting 5xc3x971013 cmxe2x88x922, 400 keV phosphor atoms, 2xc3x971012 cmxe2x88x922, 200 keV phosphor atoms, and 4xc3x971012 cmxe2x88x922, 30 keV phosphor atoms in the step of implanting atoms through the first oxide film. Such a varicap is optimized for a frequency of 17 GHz, has a tuning range of about 3 using a voltage swing of 0-3 V. The quality factor is at least 16.